FIG. 1A illustrates a conventional method for controlling a hardware queue. As shown in FIG. 1A, the hardware queue is implemented with dynamic random access memory (DRAM) 102. Data stored in the hardware queue, represented with the symbol X 104, may be pointers to other contents of a database. The hardware queue may be configured to implement a first-in first-out (FIFO) queue. The FIFO queue may be wrapped around, as indicated by arrow 106. Although a hardware queue implemented with DRAM may be lower in cost, this low cost implementation comes with tradeoffs. First, DRAMs are not efficient in handling non-sequential short data accesses, such as accessing pointers stored in a FIFO queue. In addition, comparing to other alternative solutions, the accessing time to DRAMs tends to be slower, as the accessing time may be negatively affected by the number of accesses to the DRAMs and the priority of controller of the hardware queue versus other entities that may access the DRAMs.
FIG. 1B illustrates another conventional method for controlling a hardware queue. In the example of FIG. 1B, the hardware queue is implemented with static random access memory (SRAM) 112. Data stored in the hardware queue, represented with the symbol X 114, may be pointers to other contents of a database. The hardware queue may be configured to implement a first-in first-out (FIFO) queue. The FIFO queue may be wrapped around, as indicated by arrow 116. Although a hardware queue implemented with SRAM may have cured the defect of DRAM in handling non-sequential short data accesses and has improved the access time as compared to DRAM, it comes with a cost. In general, the cost of SRAMs is numerous times higher than the cost of DRAMs. In data center applications, where millions of users may be accessing different data contents simultaneously, it would take a large number of hardware queues to support such data center applications. The cost of implementing hardware queues with SRAMs for data center applications may be prohibitively expensive.
Therefore, there is a need for methods and systems that address the issues of the conventional hardware queues described above. Specifically, there is a need for methods and systems for controlling hardware queues.